ICE devices use volatile SRAM to store configuration data. For example, a logic function with seven inputs could be implemented in eight LUT4s or two LUT6s. 5–9Ĭompared to LUT6-based architectures (such as Xilinx 7-series devices and Altera Stratix devices), a LUT4-based device is unable to implement as-complex logic functions with the same number of logic cells. The number of RAM blocks varies depending on the device. Interspersed with PLBs are blocks of RAM, each four kilobits in size. Within a PLB, each logic cell is connected to the following and preceding cell by carry logic, intended to improve the performance of constructs such as adders and subtractors. Each logic cell consists of a four-input lookup table (sometimes called a 4-LUT or LUT4) with the output connected to a D flip-flop (a 1- bit storage element). ICE65 and iCE40 devices are constructed as an array of programmable logic blocks (PLBs), where a PLB is a block of eight logic cells. See also: FPGA § Technical design, and FPGA § Architecture Architecture The architecture of iCE40 LP and HX1K devices. UltraPlus devices provide additional memory, additional processing elements, and support for newer interfaces and protocols compared to previous iCE40 Ultra/UltraLite devices. In December 2016, Lattice launched the iCE40 UltraPlus device family. The family won the 2015 Elektra Digital Semiconductor Product of the Year award. The devices in this family are claimed to operate at 30% less power than those of unspecified competitors, and are claimed to be the world's smallest FPGAs, being available in 1.4×1.4 mm packages. In February 2015, Lattice launched the iCE40 UltraLite device family. In July 2014, the iCE40 Ultra family was announced. The iCE40 LP family won the Elektra Digital Semiconductor Product of the Year award for 2012. The iCE40 LP and HX device families entered volume production the following month. In April 2012, Lattice announced that the iCE65 families would be discontinued. As part of this buyout, Lattice received the iCE brand, manufacturing capabilities with TSMC, and a licence for various patents from Kilopass Technologies, including for its XPM one-time programmable (OTP) memory technology. On 9 December 2011, SiliconBlue Technologies was acquired by Lattice Semiconductor in a $63.2 million cash buyout. The iCE40 product family was officially released in July 2011. The production of devices on a 40 nm process node was further confirmed in June 2011, when SiliconBlue received $18 million in Series D funding to bring 40 nm devices to market. In April 2011, SiliconBlue announced that it was to release new product families, code-named "Los Angeles" and "San Francisco," using a TSMC 40 nm process node. In the June of the same year, SiliconBlue closed a $15 million Series C funding round. The devices were claimed to be as much as 30% faster than iCE65 L devices while maintaining similar power consumption. In 2010, the lowest-end of the iCE65 P devices was announced by SiliconBlue. SiliconBlue also registered SiliconBlue Technologies (Hong Kong) Limited, which remains as a subsidiary of Lattice Semiconductor. In 2009, the first iCE65 L devices were shipped to customers. In October 2008, SiliconBlue raised a further $24 million in Series B capital. The devices were to be fabricated on TSMC's 65 nm CMOS process node, which SiliconBlue claimed would provide reduced power consumption compared to contemporary FPGAs from other manufacturers. In 2006, SiliconBlue was funded with $16 million in "Series A" capital, and in June 2008 announced the iCE65 L series of devices. Most notable among the founders was John Birkner, one of the inventors of programmable array logic. SiliconBlue was a start-up founded in 2005 by former employees of Actel, AMD, Lattice, Monolithic Memories, and Xilinx. The iCE brand was originally used by SiliconBlue Technologies Corporation, a former Santa Clara, California-based fabless designer of integrated circuits.
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